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dual-in-line and soic in 1 in 2 d 1 d 2 s 1 s 2 v? v+ gnd v l s 4 s 3 d 4 d 3 in 4 in 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 top view 9 dg444 dg444/445 vishay siliconix document number: 70054 s-52433?rev. f, 06-sep-99 www.vishay.com 1 quad spst cmos analog switches

low on-resistance: 50 low leakage: 80 pa low power consumption: 22 nw fast switching action?t on : 120 ns low charge injection dg211/dg212 upgrades ttl/cmos logic compatible low signal errors and distortion reduced power supply requirements faster throughput improved reliability reduced pedestal errors simple interfacing audio switching battery powered systems data acquisition sample-and-hold circuits telecommunication systems automatic test equipment single supply circuits hard disk drives

the dg444/DG445 monolithic quad analog switches are designed to provide high speed, low error switching of analog signals. the dg444 has a normally closed function. the DG445 has a normally open function. combining low power (22 nw, typ) with high speed (t on : 120 ns, typ), the dg444/DG445 are ideally suited for upgrading dg211/212 sockets. charge injection has been minimized on the drain for use in sample-and-hold circuits. to achieve high-voltage ratings and superior switching performance, the dg444/DG445 are built on vishay siliconix?s high-voltage silicon-gate process. an epitaxial layer prevents latchup. each switch conducts equally well in both directions when on, and blocks input voltages to the supply levels when off.

logic dg444 DG445 0 on off 1 off on logic ?0? 0.8 v logic ?1? 2.4 v

temp range package part number dg444dj 16-pin plastic dip DG445dj ?40 c to 85 c dg444dy 16-pin narrow soic DG445dy
dg444/445 vishay siliconix www.vishay.com 2 document number: 70054 s-52433 ? rev. f, 06-sep-99

v+ to v ? 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v ? 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v l (gnd ? 0.3 v) to (v+) + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a v s , v d (v ? ) ? 2 v to (v+) +2 v . . . . . . . . . . . . . . . . . . . . . . . . . . or 30 ma, whichever occurs first continuous current (any terminal) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . current, s or d (pulsed 1 ms, 10% duty cycle) 100 ma . . . . . . . . . . . . . . . . . . storage temperature ? 65 to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package)b 16-pin plastic dip c 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin narrow body soic d 640 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x , or in x exceeding v+ or v ? will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/ c above 75 c d. derate 8 mw/ c above 75 c

test conditions unless otherwise specified d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 15 v v l = 5 v, v in = 2.4 v, 0.8 v e temp a min b typ c max b unit analog switch analog signal range d v analog full ? 15 15 v drain-source on-resistance r ds(on) i s = ? 10 ma, v d = 8.5 v v+ = 13.5 v, v ? = ? 13.5 v room full 50 85 100 i s(off) v+ = 16.5, v ? = ? 16.5 v room full ? 0.5 ? 5 0.01 0.5 5 switch off leakage current i d(off) v+ = 16.5, v ? = ? 16.5 v v d = 15.5 v, v s = 15.5 v room full ? 0.5 ? 5 0.01 0.5 5 na channel on leakage current i d(on) v+ = 16.5 v, v ? = ? 16.5 v v s = v d = 15.5 v room full ? 0.5 ? 10 0.08 0.5 10 digital control input current v in low i il v in under test = 0.8 v all other = 2.4 v full ? 500 ? 0.01 500 input current v in high i ih v in under test = 2.4 v all other = 0.8 v full ? 500 0.01 500 na dynamic characteristics turn-on time t on room 120 250 r l = 1 k , c l = 35 pf v = 10 v, see figure 2 dg444 room 110 140 ns turn-off time t off v s = room ? 1 pc off isolation e oirr room 60 crosstalk (channel-to-channel) d x talk r l = 50 , c l = 5 pf, f = 1 mhz room 100 db source off capacitance c s(off) room 4 drain off capacitance c d(off) f = 1 mhz room 4 pf channel on capacitance c d(on) v analog = 0 v room 16 power supplies positive supply current i+ room full 0.001 1 5 negative supply current i ? v+ = 16.5 v, v ? = ? 16.5 v room full ? 1 ? 5 ? 0.0001 logic supply current i l v+ = 16.5 v, v ? = ? 16.5 v v in = 0 or 5 v room full 0.001 1 5 a ground current i gnd room full ? 1 ? 5 ? 0.001
dg444/445 vishay siliconix document number: 70054 s-52433 ? rev. f, 06-sep-99 www.vishay.com 3

test conditions unless otherwise specified d suffix ? 40 to 85 c parameter symbol v+ = 12 v, v ? = 0 v v l = 5 v, v in = 2.4 v, 0.8 v e temp a min b typ c max b unit analog switch analog signal range d v analog full 0 12 v drain-source on-resistance d r ds(on) i s = ? 10 ma, v d = 3 v, 8 v v+ = 10.8 v, v l = 5.25 v room full 100 160 200 dynamic characteristics turn-on time t on r = 1 k , c = 35 pf, v = 8 v room 300 450 turn-off time t off r l = 1 k , c l = 35 pf, v s = 8 v see figure 2 room 60 200 ns charge injection q c l = 1 nf, v gen = 6 v, r gen = 0 room 2 pc power supplies positive supply current i+ v+ = 13.2 v, v in = 0 or 5 v room full 0.001 1 5 negative supply current i ? v in = 0 or 5 v room full ? 1 ? 5 ? 0.0001 logic supply current i l v l = 5.25 v, v in = 0 or 5 v room full 0.001 1 5 a ground current i gnd v in = 0 or 5 v room full ? 1 ? 5 ? 0.001 notes: a. room = 25 c, full = as determined by the operating temperature suffix. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guaranteed by design, not subject to production test. e. v in = input voltage to perform proper function.
dg444/445 vishay siliconix www.vishay.com 4 document number: 70054 s-52433 ? rev. f, 06-sep-99

r ds(on) vs. v d and temnperature crosstak and off isolation vs. frequency source/drain leakage currents source/drain leakage currents (single 12-v supply) charge injection vs. source voltage switching threshold vs. supply voltage (pa) i , i sd (pa) i , i sd (v) th v q (pc) r ds(on) ? drain-source on-resistance ( ) (db) v d ? drain voltage (v) f ? frequency (hz) v s ? source voltage (v) v supply (v) v d or v s ? drain or source voltage (v) v d or v s ? drain or source voltage (v) 15 0 ? 15 0 20 50 30 70 80 40 60 10 25 c 85 c ? 40 c 0 c v+ = 15 v v ? = ? 15 v ? 10 ? 5510 048121620 0 3 2 1 4 v l = 7 v v l = 5 v 0 ? 20 ? 40 ? 80 ? 100 ? 60 ? 120 ? 140 v+ = 15 v v ? = ? 15 v ref. 10 dbm off isolation crosstalk 1 k 10 k 100 k 1 m 10 m 100 10 0 ? 10 ? 30 ? 10 20 0 40 50 10 30 ? 20 ? 55 15 0 ? 15 ? 100 ? 80 ? 40 ? 20 ? 60 0 20 ? 10 ? 5510 i s(off) , i d(off) i d(on) v+ = 15 v v ? = ? 15 v for i (off) , v d = ? v s 12 6 0 ? 40 ? 30 ? 10 ? 20 0 10 v+ = 12 v v ? = 0 v for i d , v s = 0 v for i s , v d = 0 v i s(off) , i d(off) i s(on) + i d(on) 24 810 c l = 1 nf v+ = 15 v v ? = ? 15 v v+ = 12 v v ? = 0 v
dg444/445 vishay siliconix document number: 70054 s-52433 ? rev. f, 06-sep-99 www.vishay.com 5

, i ? , i+, i i l gnd switching time vs. power supply voltage source/drain capacitance vs. analog voltage switching time vs. input voltage switching times vs. power supply voltage supply current vs. temperature input voltage (v) v analog ? analog voltage (v) v supply (v) v+ ? positive supply (v) temperature ( c) (pf) c s, d t (ns) t (ns) t (ns) 10 12 14 16 18 20 22 160 140 120 20 80 60 40 100 t off t on t off t on dg444 DG445 500 400 0 822 200 100 300 10 12 14 16 18 20 t on t off t on v ? = 0 v v l = 5 v t off dg444 DG445 100 ma 100 na 100 50 0 ? 55 125 i+, i gnd ? (i ? ) i l 10 ma 1 ma 10 na 1 na ? 25 25 75 100 pa 10 pa 1 pa 15 0 ? 15 0 5 15 10 20 25 ? 10 ? 5510 v+ = 15 v v ? = ? 15 v c s(off) , c d(off) c s(on) + c d(on) 160 140 120 20 25 100 80 60 40 34 v+ = 15 v v ? = ? 15 v t on t on t off dg444 DG445
dg444/445 vishay siliconix www.vishay.com 6 document number: 70054 s-52433 ? rev. f, 06-sep-99

figure 1. level shift/ drive v in v l s v+ gnd v ? d v ? v+

figure 2. switching time figure 3. charge injection 0 v logic input switch input switch output 3 v 50% 0 v v o v s t r <20 ns t f <20 ns t off t on note: logic input waveform is inverted for DG445. off on off off on off v o v o in x in x q = v o x c l (dg444) (DG445) 50% 80% 80% 10 v c l (includes fixture and stray capacitance) v ? v l in s d 3 v r l 1 k c l 35 pf v o ? 15 v gnd +5 v c l 1 nf in d v o v ? v+ s 3 v v g r g ? 15 v gnd +15 v v+ +15 v v l +5 v
dg444/445 vishay siliconix document number: 70054 s-52433 ? rev. f, 06-sep-99 www.vishay.com 7

figure 4. crosstalk figure 5. off isolation figure 6. source/drain capacitances c = 1 mf tantalum in parallel with 0.01 mf ceramic 50 d 1 v o r g = 50 s 1 +15 v ? 15 v d 2 gnd v+ v ? nc c c s 2 r l in 1 x talk isolation = 20 log v s v o 0v, 2.4 v 0v, 2.4 v v s in 2 c = rf bypass s in r l d r g = 50 v s v o 0v, 2.4 v off isolation = 20 log v s v o v+ ? 15 v gnd v ? c s d f = 1 mhz in ? 15 v gnd v ? c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent v l +5 v +15 v c +5 v v l v+ +15 v c +5 v v l

figure 7. level shifter +15 v +15 v +15 v +5 v 0 v 0 v +5 v v+ v ? gnd v in 10 k v l v out 1 / 4 dg444
dg444/445 vishay siliconix www.vishay.com 8 document number: 70054 s-52433 ? rev. f, 06-sep-99

+ 5 v ? 15 v v ? gnd dg444 or DG445 + ? v in v out gain error is determined only by the resistor tolerance. op amp offset and cmrr will limit ac- curacy of circuit. gain 1 a v = 1 gain 2 a v = 10 gain 3 a v = 20 gain 4 a v = 100 r 1 90 k r 2 5 k r 3 4 k r 4 1 k v out v in = r 1 + r 2 + r 3 + r 4 r 4 = 100 with sw 4 closed: figure 8. precision-weighted resistor programmable-gain amplifier figure 9. precision sample-and-hold +15 v v l v+ ? 15 v +15 v +15 v ? 15 v 30 pf gnd dg444 j202 j500 j507 +15 v 2n4400 + ? logic input low = sample high = hold r 1 200 k c 2 1000 pf c 1 50 pf v in v out v 1 5 m 5.1 m v 2 +5 v

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